Lab 2: Flip-Flops and Counters

Sections A: Using Set-Clear FF (R-S FF) as a Debouncer

1)

The truth table of above circuit is:

S	C	Q	Not Q
0	0	1	1
0	1	0	1
1	0	1	0
1	1	Ambiguous (Depends on the order of Input)

2) I wired the S-C flip-flop and verified the truth table above is correct. The order of the inputs are not important for all cases other then if both S and C are set to one. If S is set to HIGH first and then C, the Q will be high. However, if C is set to HIGH first and S follows, Q will be LOW. One other thing I noticed is that since the circuit is symmetric, the assignment of S and C input is arbitrary. But once one input is defined as S, the other has to be C and the Q and not Q output will also be determined accordingly.

3) I connected an SPDT toggle switch as shown above and found the switch bounces for two to three milliseconds on the oscilloscope (see sketch 1).

4) I then wired the S-C FF as a switch debouncer as shown above. I found that the switch has a much cleaner transition when the debouncer is in place as indicated in the following sketch:

Sketch #1:

Bouncing behaviour

After debouncer is added

Before debouncer is added

Scale :

5V/div

5 ms/div

5) I designed a debouner using NOR gates and used EWB to test its operation. First I wired a switch to an oscilloscope and observed the bouncing behavior of the switch.

Then I used the NOR gates to debounce the switch and observed it with the oscilloscope.

Notice the second oscilloscope output has a vertical edge as oppose to the sloped edge in the first output. The two outputs are both taken over 0.1 second interval to ensure the observation is not just an artifact caused by the difference in scale. The second output has a vertical edge because the NOR gates successfully debounce the switch.

Sections B: J-K Flip-Flop

1) and 2) I wired a 7476 JK flip-flop as shown and verified that the truth table of my circuit is the same of the accepted JK-FF’s.

3) I grounded C which holding S HIGH and saw Q became LOW and not Q became HIGH. I then grounded S while keeping C HIGH and saw Q became HIGH and not Q became LOW. It would be a bad idea to ground both S and C at the same time because the chip is not designed to handle such input. In the worst case scenario, the chip could be damaged. In less server case, the output of the chip will be ambiguous. It will vary from chip to chip depending on the minor differences among components inside.

4) I then connected two JK FF’s in series by wiring the Q output of the first JK to the CLK of the second and holding all input for the FF’s at HIGH. I applied a 2kHz wave at the input and observed the following output at the:

Q1:

Q2:

Input:

Scale :

5V/div

0.1 ms/div

The output is exactly what I expected. It is because since all input is held HIGH, both JK will toggle. The rates they toggle are dependent upon the CLK input. Because the chip is falling edge triggered, the first JK will change state whenever the input has a falling edge and the second JK will change state whenever Q1 has a falling edge.

One peculiarity I observed is the fact that the signal dropped about 1 volt for each JK it go through (i.e. the input HIGH is at 5volts, Q1 HIGH is at 4 volts and Q2 HIGH is at 3 volts.) This observation is contrary to what I expected because the output HIGH voltage is supposed to be supplied by Vcc connected to pin 5. Since both JK is on the same chip, both of them should have output HIGH at 5 volts. I am not too sure how to explain this observation and believe it is due to the internal design of the chip that I am not aware of.

5) The frequency of the first FF output was 1/(10div*0.1ms/div)=1kHz (half of the input signal frequency) and the frequency of the second FF output is 1/(20div*0.1ms/div) = 500Hz (half of Q1 frequency). It was what I expected because the way the JK aare connected together as explained in step 4.

6) Using the clock signal on the digiboard as input, I increased the frequency of the clock until the JK2 stop flip flopping. Below are the sketches of oscilloscope display:

Scale:

5V/div

20us/div

Q2 just before stop flip flopping

Clock:

Scale:

5V/div

20us/div

Q2 right after stop flip flopping

Clock:

From the above observation, it seems like the limiting frequency of JK2 is 1/(1.9div*20us/div) = 26kHz

However, I realized that conclusion is wrong because Q2 only appear to stop flip flopping because the oscilloscope is set to trigger from the input clock signal. When I switch the oscilloscope to trigger from Q2 signal, I found that the clock frequency can increase much more before JK2 stop flip flopping.

I used the function generator’s square wave as clock signal because the clock output from digiboard was not fast enough. Following are the oscilloscope observations:

2V/div

0.1us/div

2V/div

0.2us/div

Clock:

Q2 before stop flip flopping

Q2 right after stop flip flopping

Clock:

The clock signal had a lot of oscillatory behavior because it was produced at such a high frequency. The FF still responded to the clock signal despite the oscillatory behavior unit it hit the limiting frequency. The limiting frequency of JK2 is 1/(3.2div*0.1us/div) = 3.1MHz.

Clock signal at 4MHz

Q1:

2V/div

0.1us/div

I found that the limiting frequency for JK 1 is so high that the function generator could not generate high enough frequency signal for the JK to stop responding.

I expected that Q2 should have a higher limiting frequency than Q1 because Q1 is used to trigger JK2 and Q1 should have half the frequency as input clock signal. One reason I could think of that might contribute to the experimental result is that the clock signal from function generator might have more power to drive JK1 but Q1 didn’t have enough power to drive JK2.

Sections C: Mod-8 and Mod-7 Counters

1) I wired the above Mod-8 counter and observed how it worked. The first JK would toggle whenever it was triggered by a clock signal because both its J and K inputs were both held HIGH. JK2 would toggle only when Q1 was HIGH (therefore once for every two clock pulses) and its state didn’t change otherwise. Q1 served as the least significant bit and Q2 is the middle bit. JK3 would toggle when both Q1 and Q2 are HIGH (because of the two NAND gates) and it served as the most significant bit.

2) This is the output combinations and the logic levels present at each JK input:

L3	L2	L1	J1	K1	J2	K2	J3	K3
0	0	0	1	1	0	0	0	0
0	0	1	1	1	1	1	0	0
0	1	0	1	1	0	0	0	0
0	1	1	1	1	1	1	1	1
1	0	0	1	1	0	0	0	0
1	0	1	1	1	1	1	0	0
1	1	0	1	1	0	0	0	0
1	1	1	1	1	1	1	1	1

3) By adding the following adjustment, I was able to make the Mod-8 counter into a Mod-7 counter:

The AND gate and NAND gate at the bottom of the diagram ensure that the CLEAR input of the three JK is held HIGH until all three Q output are HIGH. At that time, the NAND gate will output zero, and cause all three JK are cleared and the counting restart at 000.

Although this method work to make the counting to turn over from 110 to 000. There is a small time where the output is actually 111. In the oscilloscope one will see that as a “glitch” and it could not be get rid of in this particular design of the Mod-7 counter.

Sections D: Presettable counter

In this section, I tested the asynchronous PRESET feature of the JK FF. Attached three switches to the PRESET input and grounding them to preset the JK. I tried different preset combination and found the following counting responses:

	Combo 1			Combo 2			Combo 3			Combo 4			Combo 5
Starting value	0	1	0	1	1	0	1	0	0	1	0	1	0	0	1
Value after 1 count	0	1	1	1	1	1	1	0	1	1	1	1	0	1	1
“ after 2 “	1	1	0				1	1	0				1	0	1
“after 3”	1	1	1				1	1	1				1	1	1

As can be seen from the table, the PRESET feature worked, but the counting did not necessary go up with the correct increment. It was what I expected because some of the outputs are held HIGH constantly independent of the other logic in the counter. I should have turned off the PRESET input (by connecting it to 5V) after the counter count pass the bit and see if the counter will continue to count up to 111 with the correct increment. But I didn’t have the chance to do that during the lab.

Section E: Frequency Detector

1) I built the above circuit and soldered the components together. However, I then realized that the potentiometer would not change resistance. Therefore, my circuit was limited to detect only one frequency (1/(3.1div*0.5ms)=645Hz).

2) Because my potentiometer didn’t work, the output of OS has a fixed period at T = 1/645Hz = 1.55ms length.

3) My circuit responded to input frequency lower then 645Hz but outputting a square wave signal. The square wave signal has approximately half the frequency of the input signal.

4) When the input frequency is higher than 645Hz, my circuit output a constant voltage (either zero or 5 volts depending what the state of Q is right before the input frequency crossed 645Hz). It is what I expected because the output of OS will stop alternating when the input frequency crossed 645Hz and the JK FF will stop toggling.

5) When I closed S1, the output of the circuit is always LOW no matter what frequency the input is. It is what I expect because the CLR feature on JK FF is activated when S1 is closed.

6) If I used NRT One-shot, the threshold frequency not be exactly what is determined by the C and R value attached to the OS. It is because the OS will ignore any input until T is passed. If the input pulse come right after the OS could be trigger again, then the output is LOW However, there the input pulses come too early or too late, the output of the circuit will still toggle even the input frequency passed the threshold frequency. In short, the circuit will not work as it is intended to.